CDC339中文资料具有三态输出的 1:8 TTL 时钟驱动器数据手册TI规格书

描述 Description

The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.

When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions of CLK. Taking CLR low asynchronously resets the Q outputs to the low level. When OE is high, the outputs are in the high-impedance state.

The CDC339 is characterized for operation from −40°C to 85°C.



The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.

When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions of CLK. Taking CLR low asynchronously resets the Q outputs to the low level. When OE is high, the outputs are in the high-impedance state.

The CDC339 is characterized for operation from −40°C to 85°C.

特性 Features

• Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
• Distributes One Clock Input to Eight Outputs
• Four Half-Frequency Outputs
• Distributed VCC and Ground Pins Reduce Switching Noise
• State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation
• Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages