CDC2586中文资料具有 1/2x、1x 及 2x 频率选项的 3.3V PLL 时钟驱动器数据手册TI规格书

描述 Description

The CDC2586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured for half-frequency operation. Each output has an internal 26- series resistor that improves the signal integrity at the load. The CDC2586 operates at nominal 3.3-V VCC.
The feedback input (FBIN) synchronizes the output clocks in frequency and phase to CLKIN. One of the twelve output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as feedback is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs (SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN frequency depending on which output is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at CLKIN.
Output-enable (OE\\) provides output control. When OE\\ is high, the outputs are in the high-impedance state. When OE\\ is low, the outputs are active. TEST is used for factory testing of the device and can be used to bypass the PLL. TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs, the CDC2586 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2586 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, enabling of the PLL via TEST, and upon enable of all outputs via OE\\.
The CDC2586 is characterized for operation from 0°C to 70°C.

特性 Features

·Low Output Skew for Clock-Distribution and Clock-Generation Applications ·Operates at 3.3-V VCC ·Distributes One Clock Input to 12 Outputs ·Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency ·No External RC Network Required ·External Feedback (FBIN) Synchronizes the Outputs to the Clock Input ·Application for Synchronous DRAM, High-Speed Microprocessor ·TTL-Compatible Inputs and Outputs ·Outputs Have Internal 26- Series Resistors to Dampen Transmission-Line Effects ·State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation ·Distributed VCC and Ground Pins Reduce Switching Noise ·Packaged in 52-Pin Thin Quad Flat Package>EPIC-IIB is a trademark of Texas Instruments Incorporated.