3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On-

文件：348.1 Kbytes 页数：16 Pages

TI

德州仪器

3.3V PHASE-LOCK LOOP CLOCK DRIVER

文件：490.18 Kbytes 页数：15 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：143.79 Kbytes 页数：10 Pages

TI

德州仪器

丝印：CDC2536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On-

文件：348.1 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CDC2536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On-

文件：348.1 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CDC2536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On-

文件：348.1 Kbytes 页数：16 Pages

TI

德州仪器

具有 1/2x、1x 和 2x 频率选项的 125MHz、3.3V PLL 时钟驱动器

The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors op • Low Output Skew for Clock-Distribution and Clock-Generation Applications\n• Distributes One Clock Input to Six Outputs\n• No External RC Network Required\n• External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input\n• TTL-Compatible Inputs and Outputs\n• State-of-the-Art E;

TI

德州仪器

3.3V PHASE-LOCK LOOP CLOCK DRIVER

文件：490.18 Kbytes 页数：15 Pages

TI

德州仪器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：143.79 Kbytes 页数：10 Pages

TI

德州仪器

3.3V PHASE-LOCK LOOP CLOCK DRIVER

文件：490.18 Kbytes 页数：15 Pages

TI

德州仪器