丝印：CD74HCT74E；Package：PDIP；CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

文件：1.1948 Mbytes 页数：28 Pages

TI

德州仪器

丝印：CD74HCT74E；Package：PDIP；CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

文件：1.1948 Mbytes 页数：28 Pages

TI

德州仪器

丝印：CD74HCT74E；Package：PDIP；CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

文件：1.1948 Mbytes 页数：28 Pages

TI

德州仪器

丝印：CD74HCT74E；Package：PDIP；CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

文件：1.1948 Mbytes 页数：28 Pages

TI

德州仪器

Dual D Flip-Flop with Set and Reset Positive-Edge Trigger

文件：43.47 Kbytes 页数：8 Pages

TI

德州仪器

Dual D Flip-Flop with Set and Reset Positive-Edge Trigger

文件：276.3 Kbytes 页数：12 Pages

TI

德州仪器

Dual D Flip-Flop with Set and Reset

文件：628.26 Kbytes 页数：17 Pages

TI

德州仪器