CD74HC297

High-Speed CMOS Logic Digital Phase-Locked Loop

Features •DigitalDesignAvoidsAnalogCompensationErrors •EasilyCascadableforHigherOrderLoops •UsefulFrequencyRange -K-Clock..........................DCto55MHz(Typ) -I/D-Clock....................DCto35MHz(Typ) •DynamicallyV

CD74HC297

高速 CMOS 逻辑数字锁相环; • Digital Design Avoids Analog Compensation Errors\n• Easily Cascadable for Higher Order Loops\n• Useful Frequency Range \n - K-Clock...DC to 55MHz (Typ)\n• I/D-Clock...DC to 35MHz (Typ)\n• Dynamically Variable Bandwidth\n• Very Narrow Bandwidth Attainable\n• Power-On Reset\n• Output Capability \n - Standard...XORPDOUT, ECPDOUT\n• Bus Driver...I/DOUT\n• Fanout (Over Temperature Range) \n - Standard Outputs...10 LSTTL Loads\n• Bus Driver Outputs...15 LSTTL Loads\n• Balanced Propagation Delay and Transition Times\n• Significant Power Reduction Compared to LSTTL Logic ICs\n• ’HC297 Types \n - Operation Voltage...2 to 6V\n• High Noise Immunity NIL = 30%, NIH = 30% of VCC at 5V\n• CD74HCT297 Types \n - Operation Voltage...4.5 to 5.5V\n• Direct LSTTL Input Logic Compatibility VIL =0.8V (Max), VIH =2V (Min)\n• CMOS Input Compatibility II 1µA at VOL , VOH\nData sheet acquired from Harris Semiconductor;

The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL).\n These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops.\n Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range.\n Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops.\n The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked-loop.\n The ’HC297 and CD74HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (DPLL) is not affected by VCC and temperature variations but depends solely on accuracies of the K-clock and loop propagation delays.\n \n

CD74HC297

High-Speed CMOS Logic Digital Phase-Locked-Loop

CD74HC297

High-Speed CMOS Logic Digital Phase-Locked Loop

CD74HC297E

丝印：CD74HC297E；Package：PDIP；High-Speed CMOS Logic Digital Phase-Locked Loop

Features •DigitalDesignAvoidsAnalogCompensationErrors •EasilyCascadableforHigherOrderLoops •UsefulFrequencyRange -K-Clock..........................DCto55MHz(Typ) -I/D-Clock....................DCto35MHz(Typ) •DynamicallyV

CD74HC297E.A

丝印：CD74HC297E；Package：PDIP；High-Speed CMOS Logic Digital Phase-Locked Loop

Features •DigitalDesignAvoidsAnalogCompensationErrors •EasilyCascadableforHigherOrderLoops •UsefulFrequencyRange -K-Clock..........................DCto55MHz(Typ) -I/D-Clock....................DCto35MHz(Typ) •DynamicallyV

CD74HC297E

High-Speed CMOS Logic Digital Phase-Locked Loop

CD74HC297E

High-Speed CMOS Logic Digital Phase-Locked Loop

CD74HC297EE4

High-Speed CMOS Logic Digital Phase-Locked Loop

CD74HC297E

Package：16-DIP（0.300"，7.62mm）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC DIGITAL PLL 16-DIP