CDx4AC08 Quadruple 2-Input Positive-and Gates

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Speed of bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays • Buffered inputs • ±24mA output drive current - Fanout to 15 F dev

文件：1.2263 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CD54AC08F3A；Package：CDIP；CDx4AC08 Quadruple 2-Input Positive-and Gates

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Speed of bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays • Buffered inputs • ±24mA output drive current - Fanout to 15 F dev

文件：1.2263 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CD54AC08F3A；Package：CDIP；CDx4AC08 Quadruple 2-Input Positive-and Gates

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Speed of bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays • Buffered inputs • ±24mA output drive current - Fanout to 15 F dev

文件：1.2263 Mbytes 页数：23 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset

Description The CD54AC109/3A and CD54ACT109/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. These flip-flops have independent J, K, Set, Reset and Clock inputs and Q and Q outputs. The CD54AC109/3A and CD54ACT109/3A changes state on the posi

文件：10.39 Kbytes 页数：1 Pages

INTERSIL

Dual J-K Flip-Flop with Set and Reset

Description The CD54AC109/3A and CD54ACT109/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. These flip-flops have independent J, K, Set, Reset and Clock inputs and Q and Q outputs. The CD54AC109/3A and CD54ACT109/3A changes state on the posi

文件：10.39 Kbytes 页数：1 Pages

INTERSIL

CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Speed of bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays • ±24mA output drive current – Fanout to 15 F devices • SCR-latchup

文件：1.09024 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD54AC109F3A；Package：CDIP；CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Speed of bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays • ±24mA output drive current – Fanout to 15 F devices • SCR-latchup

文件：1.09024 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD54AC109F3A；Package：CDIP；CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Speed of bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays • ±24mA output drive current – Fanout to 15 F devices • SCR-latchup

文件：1.09024 Mbytes 页数：22 Pages

TI

德州仪器

Dual “J-K” Flip-Flop with Set and Reset

Description The CD54AC112/3A and CD54ACT112/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. The CD54AC112/3A and CD54ACT112/3A are supplied in 16 lead dual-in-line ceramic packages (F suffix).

文件：10.3 Kbytes 页数：1 Pages

INTERSIL

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Pro

文件：426.59 Kbytes 页数：15 Pages

TI

德州仪器