CD54AC109

Dual J-K Flip-Flop with Set and Reset

Description TheCD54AC109/3AandCD54ACT109/3Aaredual“J-K”flip-flopswithsetandresetthatutilizetheHarrisAdvancedCMOSLogictechnology.Theseflip-flopshaveindependentJ,K,Set,ResetandClockinputsandQandQoutputs.TheCD54AC109/3AandCD54ACT109/3Achangesstateontheposi

CD54AC112

Dual “J-K” Flip-Flop with Set and Reset

Description TheCD54AC112/3AandCD54ACT112/3Aaredual“J-K”flip-flopswithsetandresetthatutilizetheHarrisAdvancedCMOSLogictechnology. TheCD54AC112/3AandCD54ACT112/3Aaresuppliedin16leaddual-in-lineceramicpackages(Fsuffix).

CD54AC112

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

ACTypesFeature1.5-Vto5.5-VOperation andBalancedNoiseImmunityat30%ofthe SupplyVoltage SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSPro

CD54AC112F3A

丝印：CD54AC112F3A；Package：CDIP；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

ACTypesFeature1.5-Vto5.5-VOperation andBalancedNoiseImmunityat30%ofthe SupplyVoltage SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSPro

CD54AC112F3A.A

丝印：CD54AC112F3A；Package：CDIP；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

ACTypesFeature1.5-Vto5.5-VOperation andBalancedNoiseImmunityat30%ofthe SupplyVoltage SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays ±24-mAOutputDriveCurrent –Fanoutto15FDevices SCR-Latchup-ResistantCMOSPro

CD54AC113A

Dual “J-K” Flip-Flop with Set and Reset

Description TheCD54AC112/3AandCD54ACT112/3Aaredual“J-K”flip-flopswithsetandresetthatutilizetheHarrisAdvancedCMOSLogictechnology. TheCD54AC112/3AandCD54ACT112/3Aaresuppliedin16leaddual-in-lineceramicpackages(Fsuffix).

CD54AC138

CDx4AC138 3-Line to 8-Line Decoders/Demultiplexers

1Features •ACtypesfeature1.5Vto5.5Voperationand balancednoiseimmunityat30ofthesupply voltage •SpeedofbipolarF,AS,andS,withsignificantly reducedpowerconsumption •Designedspecificallyforhigh-speedmemory decodersanddata-transmissionsystems •Incorporatethre

CD54AC138_V01

CDx4AC138 3-Line to 8-Line Decoders/Demultiplexers

1Features •ACtypesfeature1.5Vto5.5Voperationand balancednoiseimmunityat30ofthesupply voltage •SpeedofbipolarF,AS,andS,withsignificantly reducedpowerconsumption •Designedspecificallyforhigh-speedmemory decodersanddata-transmissionsystems •Incorporatethre

CD54AC138F3A

丝印：CD54AC138F3A；Package：CDIP；CDx4AC138 3-Line to 8-Line Decoders/Demultiplexers

1Features •ACtypesfeature1.5Vto5.5Voperationand balancednoiseimmunityat30ofthesupply voltage •SpeedofbipolarF,AS,andS,withsignificantly reducedpowerconsumption •Designedspecificallyforhigh-speedmemory decodersanddata-transmissionsystems •Incorporatethre

CD54AC139

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

ACTypesFeature1.5-Vto5.5-VOperation andBalancedNoiseImmunityat30%ofthe SupplyVoltage BufferedInputs IncorporateTwoEnableInputstoSimplify Cascadingand/orDataReception SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagation