丝印：CD4514BF；Package：CDIP；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4514BF；Package：CDIP；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4514BF3A；Package：CDIP；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4514BF3A；Package：CDIP；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4514BF；Package：CDIP；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4514BF；Package：CDIP；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4514BF3A；Package：CDIP；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

丝印：CD4514BF3A；Package：CDIP；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

文件：643.69 Kbytes 页数：16 Pages

TI

德州仪器

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：222.79 Kbytes 页数：12 Pages

TI

德州仪器

Cmos 4-Bit Latch/4-to-16 Line Decoders

文件：1.026599 Mbytes 页数：15 Pages

TI

德州仪器