CD4076BM.A

丝印：CD4076BM；Package：SOIC；CMOS 4-Bit D-Type Registers

Features: ®Three-statsoutputs ®inputdisabledwithoutgatingtheclock ®Gatedoutputcontrollinesfor enablingordisablingtheoutputs ®Standardized,symmetricaloutput characteristics ®100%testedforquiescentcurrentat20V ®Maximuminputcurrentof1yAat18Vover full

CD4076B-MIL

CMOS 4-Bit D-Type Registers

Features: ®Three-statsoutputs ®inputdisabledwithoutgatingtheclock ®Gatedoutputcontrollinesfor enablingordisablingtheoutputs ®Standardized,symmetricaloutput characteristics ®100%testedforquiescentcurrentat20V ®Maximuminputcurrentof1yAat18Vover full

CD4076B-MIL

具有时钟和三态输出的 CMOS 4 位 D 类寄存器; • Three-state outputs\n• Input disabled without gating the clock\n• Gated output control lines for enabling or disabling the outputs\n• Standardized, symmetrical output characteristics\n• 100% tested for quiescent current at 20 V\n• Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C\n• Noise margin over full package temperature range: \n - 1 V at VDD = 5 V\n• 2 V at VDD = 10 V\n• 2.5 V at VDD = 15 V\n• 5-V, 10-V, and 15-V parametric ratings\n• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’Series CMOS Devices\"\n Data sheet acquired from Harris Semiconductor.;

CD4076B types are four-bit registers consisting of D-type flip-flops that feature three-state outputs. DataDisable inputs are provided to control the entry of data into the flip-flops. When both Data Disable inputs arelow, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the clockinput. Output Disable inputs are also provided. When the Output Disable inputs are both low, the normal logic statesof the four outputs are available to the load. The outputs are disabled independently of the clock by a high logiclevel at either Output Disable input, and present a high impedance.\n The CD4076B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).\n \n

CD4076BMS

CMOS 4 -Bit D-Type Register; • High Voltage Type (20V Rating) \n• Three State Outputs \n• Input Disabled Without Gating the Clock \n• Gated Output Control Lines for Enabling or Disabling the Outputs \n• Standardized Symmetrical Output Characteristics \n• 100% Tested for Quiescent Current at 20V \n• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC \n• Noise Margin (Over Full Package/Temperature Range) \n• 1V at VDD = 5V \n• 2V at VDD = 10V \n• 2.5V at VDD = 15V \n• 5V, 10V and 15V Parametric Ratings \n• Meets All Requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of 'B' Series CMOS Devices\"\n;

CD4076BMS types are four-bit registers consisting of D-type flip-flops that feature three-state outputs. Data Disable inputs are provided to control the entry of data into the flip-flops. When both Data Disable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the clock input. Output Disable inputs are also provided. When the Output Disable inputs are both low, the normal logic states of the four outputs are available to the load. The outputs are disabled independently of the clock by a high logic level at either Output Disable input, and present a high impedance.\nThe CD4076BMS is supplied in these 16 lead outline packages:\nBraze Seal DIP H4T Frit Seal DIP H1E Ceramic Flatpack H6W

CD4076BMS

CMOS 4 -Bit D-Type Registers

Description CD4076BMStypesarefour-bitregistersconsistingofD-typeflip-flopsthatfeaturethree-stateoutputs.DataDisableinputsareprovidedtocontroltheentryofdataintotheflip-flops.WhenbothDataDisableinputsarelow,dataattheDinputsareloadedintotheirrespectivefl

CD4076BMS

CMOS 4 -Bit D-Type Registers

Features •HighVoltageType(20VRating) •ThreeStateOutputs •InputDisabledWithoutGatingtheClock •GatedOutputControlLinesforEnablingorDisabling theOutputs •StandardizedSymmetricalOutputCharacteristics •100TestedforQuiescentCurrentat20V •MaximumInputCurrento

CD4076BMT

丝印：CD4076BM；Package：SOIC；CMOS 4-Bit D-Type Registers

Features: ®Three-statsoutputs ®inputdisabledwithoutgatingtheclock ®Gatedoutputcontrollinesfor enablingordisablingtheoutputs ®Standardized,symmetricaloutput characteristics ®100%testedforquiescentcurrentat20V ®Maximuminputcurrentof1yAat18Vover full

CD4076BMT.A

丝印：CD4076BM；Package：SOIC；CMOS 4-Bit D-Type Registers

Features: ®Three-statsoutputs ®inputdisabledwithoutgatingtheclock ®Gatedoutputcontrollinesfor enablingordisablingtheoutputs ®Standardized,symmetricaloutput characteristics ®100%testedforquiescentcurrentat20V ®Maximuminputcurrentof1yAat18Vover full

CD4076B

CMOS 4-BIT D-TYPE REGISTERS

CD4076B

CMOS 4-Bit D-type Registers