丝印：CM011B；Package：TSSOP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CM011B；Package：TSSOP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CM011B；Package：TSSOP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CM011B；Package：TSSOP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

CMOS Quad 2-Input NAND Gate

Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of

文件：29.89 Kbytes 页数：3 Pages

INTERSIL

CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

文件：978 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD4011UBE；Package：PDIP；CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

文件：978 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD4011UBE；Package：PDIP；CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

文件：978 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD4011UBE；Package：PDIP；CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

文件：978 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD4011UBF；Package：CDIP；CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

文件：978 Kbytes 页数：20 Pages

TI

德州仪器