丝印：CD40110BE；Package：PDIP；CMOS Decade Up-Down Counter/Latch/Display Driver

Features Separate clock-up and clock-down lines Capable of driving common cathode LEDs and other displays directly Allows cascading without any external circuitry 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package- temperatu

文件：487.38 Kbytes 页数：13 Pages

TI

德州仪器

CMOS HIGH-SPEED 8-BIT BIDIRECTIONAL CMOS/TTL INTERFACE LEVEL CONVERTER

文件：382.89 Kbytes 页数：6 Pages

HARRIS

CMOS HIGH-SPEED 8-BIT BIDIRECTIONAL CMOS/TTL INTERFACE LEVEL CONVERTER

文件：382.89 Kbytes 页数：6 Pages

HARRIS

Programmable Dual 4-Bit Terminator

Features: One standard “8” output will drive eight terminator circuits. Will terminate a CMOS data bus with up to 40 B~series inputs inputs or 3-stats outputs connected at Vop of 5 V. Input terminals protected by standard “B series ESD protection network. Preserves final logic state. Outp

文件：327.07 Kbytes 页数：8 Pages

TI

德州仪器

丝印：CD40117BE；Package：PDIP；Programmable Dual 4-Bit Terminator

Features: One standard “8” output will drive eight terminator circuits. Will terminate a CMOS data bus with up to 40 B~series inputs inputs or 3-stats outputs connected at Vop of 5 V. Input terminals protected by standard “B series ESD protection network. Preserves final logic state. Outp

文件：327.07 Kbytes 页数：8 Pages

TI

德州仪器

丝印：CD40117BE；Package：PDIP；Programmable Dual 4-Bit Terminator

Features: One standard “8” output will drive eight terminator circuits. Will terminate a CMOS data bus with up to 40 B~series inputs inputs or 3-stats outputs connected at Vop of 5 V. Input terminals protected by standard “B series ESD protection network. Preserves final logic state. Outp

文件：327.07 Kbytes 页数：8 Pages

TI

德州仪器

CMOS NAND Gates

Features: Quiescent current specified to 15 V Maximum input leakage of 1 uA at 15 V (full package-temperature range) 1-V noise margin (full package-temperature range)

文件：550.23 Kbytes 页数：10 Pages

TI

德州仪器

丝印：CD4011AD3；Package：CDIPSB；CMOS NAND Gates

Features: Quiescent current specified to 15 V Maximum input leakage of 1 uA at 15 V (full package-temperature range) 1-V noise margin (full package-temperature range)

文件：550.23 Kbytes 页数：10 Pages

TI

德州仪器

丝印：CD4011AD3；Package：CDIPSB；CMOS NAND Gates

Features: Quiescent current specified to 15 V Maximum input leakage of 1 uA at 15 V (full package-temperature range) 1-V noise margin (full package-temperature range)

文件：550.23 Kbytes 页数：10 Pages

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器