CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

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德州仪器

CMOS 8-Stage Presettable Synchronous Down Counters

Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is config ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has c

文件：166.83 Kbytes 页数：13 Pages

INTERSIL

丝印：CD40103B；Package：SOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD40103B；Package：SOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CM0103B；Package：TSSOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CM0103B；Package：TSSOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

CMOS 4-Bit Bidirectional Universal Shift Register

Description The CD40104BMS is a universal shift register featuring parallel inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial inputs, and a high impedance third output state allowing the device to be used in bus organized systems. In the parallel load mode (S0 and S1 are high), dat

文件：129.88 Kbytes 页数：10 Pages

INTERSIL

CMOS FIFO Register

Features • 4 Bits x 16 Words • High Voltage Type (20V Rating) • Independent Asynchronous Inputs and Outputs • 3-State Outputs • Expandable in Either Direction • Status Indicators on Input and Output • Reset Capability • Standardized Symmetrical Output Characteristics • 1

文件：116.54 Kbytes 页数：10 Pages

INTERSIL

CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

文件：512.51 Kbytes 页数：11 Pages

TI

德州仪器

丝印：CD40105BE；Package：PDIP；CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

文件：512.51 Kbytes 页数：11 Pages

TI

德州仪器