丝印：CD40103BF3A；Package：CDIP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD40103B；Package：SOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD40103B；Package：SOP；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

文件：1.00908 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD40105BE；Package：PDIP；CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

文件：512.51 Kbytes 页数：11 Pages

TI

德州仪器

丝印：CD40105BE；Package：PDIP；CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

文件：512.51 Kbytes 页数：11 Pages

TI

德州仪器

丝印：CD40105BF；Package：CDIP；CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

文件：512.51 Kbytes 页数：11 Pages

TI

德州仪器

丝印：CD40105BF；Package：CDIP；CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

文件：512.51 Kbytes 页数：11 Pages

TI

德州仪器

丝印：CD40105BF3A；Package：CDIP；CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

文件：512.51 Kbytes 页数：11 Pages

TI

德州仪器

丝印：CD40105BF3A；Package：CDIP；CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

文件：512.51 Kbytes 页数：11 Pages

TI

德州仪器

丝印：CD40106BE；Package：PDIP；CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

文件：1.14479 Mbytes 页数：35 Pages

TI

德州仪器