CDC536DBR.B

Marking：CDC536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES ·Low-OutputSkewforClock-Distributionand Clock-GenerationApplications ·Operatesat3.3-VVCC ·DistributesOneClockInputtoSixOutputs ·OneSelectInputConfiguresThreeOutputsto OperateatOne-HalforDoubletheInput Frequency ·NoExternalRCNetworkRequired ·Ext

CDCDB2000ENPPR

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter:

CDCDB2000ENPPT

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter:

CDCDB2000NPPR

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter:

CDCDB2000NPPR

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter:

CDCDB2000NPPT

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter:

CDCDB2000NPPT

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter:

CDCDB803ERSLR

Marking：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1Features •8LP-HCSLoutputswithprogrammableintegrated 85-Ω(default)or100-Ωdifferentialoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterPCIEGen6filter:20fs, RMS(maximum) •AdditivephasejitterafterPCIEGen5filter:25fs, RMS(

CDCDB803ERSLT

Marking：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1Features •8LP-HCSLoutputswithprogrammableintegrated 85-Ω(default)or100-Ωdifferentialoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterPCIEGen6filter:20fs, RMS(maximum) •AdditivephasejitterafterPCIEGen5filter:25fs, RMS(

CDCDB803RSLR

Marking：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1Features •8LP-HCSLoutputswithprogrammableintegrated 85-Ω(default)or100-Ωdifferentialoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterPCIEGen6filter:20fs, RMS(maximum) •AdditivephasejitterafterPCIEGen5filter:25fs, RMS(