CDC203DWG4

Marking：CDC203；Package：SOIC；3.3-V HEX INVERTER/CLOCK DRIVER

Replaces74AC11203 Low-SkewPropagationDelay SpecificationsforClockDriver Applications Operatesat3.3-VVCC Flow-ThroughArchitectureOptimizes PCBLayout Center-PinVCCandGNDPin ConfigurationsMinimizeHigh-Speed SwitchingNoise EPIC(Enhanced-PerformanceImplanted CMOS)1-μm

CDC204DW

Marking：CDC204；Package：SOIC；HEX INVERTER/CLOCK DRIVER

CDC204Replaces74AC11204 Low-SkewPropagationDelay SpecificationsforClock-DriverApplications CMOS-CompatibleInputsandOutputs Flow-ThroughArchitectureOptimizes PCBLayout Center-PinVCCandGNDPin ConfigurationsMinimizeHigh-Speed SwitchingNoise EPICE(Enhanced-PerformanceIm

CDC204DW.A

Marking：CDC204；Package：SOIC；HEX INVERTER/CLOCK DRIVER

CDC204Replaces74AC11204 Low-SkewPropagationDelay SpecificationsforClock-DriverApplications CMOS-CompatibleInputsandOutputs Flow-ThroughArchitectureOptimizes PCBLayout Center-PinVCCandGNDPin ConfigurationsMinimizeHigh-Speed SwitchingNoise EPICE(Enhanced-PerformanceIm

CDC204DWG4

Marking：CDC204；Package：SOIC；HEX INVERTER/CLOCK DRIVER

CDC204Replaces74AC11204 Low-SkewPropagationDelay SpecificationsforClock-DriverApplications CMOS-CompatibleInputsandOutputs Flow-ThroughArchitectureOptimizes PCBLayout Center-PinVCCandGNDPin ConfigurationsMinimizeHigh-Speed SwitchingNoise EPICE(Enhanced-PerformanceIm

CDC2351DW

Marking：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

LowOutputSkew,LowPulseSkewfor Clock-DistributionandClock-Generation Applications Operatesat3.3-VVCC LVTTL-CompatibleInputsandOutputs SupportsMixed-ModeSignalOperation (5-VInputandOutputVoltagesWith3.3-V VCC) DistributesOneClockInputtoTenOutputs OutputsHaveIn

CDC2351DW.B

Marking：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

LowOutputSkew,LowPulseSkewfor Clock-DistributionandClock-Generation Applications Operatesat3.3-VVCC LVTTL-CompatibleInputsandOutputs SupportsMixed-ModeSignalOperation (5-VInputandOutputVoltagesWith3.3-V VCC) DistributesOneClockInputtoTenOutputs OutputsHaveIn

CDC2351DWR

Marking：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

LowOutputSkew,LowPulseSkewfor Clock-DistributionandClock-Generation Applications Operatesat3.3-VVCC LVTTL-CompatibleInputsandOutputs SupportsMixed-ModeSignalOperation (5-VInputandOutputVoltagesWith3.3-V VCC) DistributesOneClockInputtoTenOutputs OutputsHaveIn

CDC2351DWR.B

Marking：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

LowOutputSkew,LowPulseSkewfor Clock-DistributionandClock-Generation Applications Operatesat3.3-VVCC LVTTL-CompatibleInputsandOutputs SupportsMixed-ModeSignalOperation (5-VInputandOutputVoltagesWith3.3-V VCC) DistributesOneClockInputtoTenOutputs OutputsHaveIn

CDC2351DWRG4

Marking：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

LowOutputSkew,LowPulseSkewfor Clock-DistributionandClock-Generation Applications Operatesat3.3-VVCC LVTTL-CompatibleInputsandOutputs SupportsMixed-ModeSignalOperation (5-VInputandOutputVoltagesWith3.3-V VCC) DistributesOneClockInputtoTenOutputs OutputsHaveIn

CDC319DB

Marking：CDC319；Package：SSOP；1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

High-Speed,Low-Skew1-to-10ClockBuffer forSDRAM(SynchronousDRAM)Clock BufferingApplications OutputSkew,tsk(o),LessThan250ps PulseSkew,tsk(p),LessThan500ps SupportsuptoTwoUnbufferedSDRAM DIMMs(DualInlineMemoryModules) I2CSerialInterfaceProvidesIndividual Ena