ECL/PECL 1:9 Differential Clock Driver

DESCRIPTION The AZ10/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q¯ outputs HIGH.

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1:9 Differential Clock Driver

[ARIZONA MICROTEK, INC.] DESCRIPTION The AZ10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or single-ended if the VBB output is used. The signal is fanned-out to 9 identical differential

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ECL/PECL 1:9 Differential Clock Driver

DESCRIPTION The AZ10/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q¯ outputs HIGH.

文件：91.66 Kbytes 页数：6 Pages

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ECL/PECL Quint Differential Line Receiver

DESCRIPTION The AZ10/100E116 is a quint differential line receiver with emitter-follower outputs. The E116 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For single-ended input applications, the VBB reference should be connected to one side of the

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ECL/PECL 4-bit D Flip-Flop

DESCRIPTION The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CE ¯¯ n) inputs for clocking. FEATURES • 1100 MHz Min. Toggle Frequency • Differential Outp

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ECL/PECL 4-bit D Flip-Flop

DESCRIPTION The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CE ¯¯ n) inputs for clocking. FEATURES • 1100 MHz Min. Toggle Frequency • Differential Outp

文件：76.08 Kbytes 页数：6 Pages

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ECL/PECL 9-bit Shift Register

DESCRIPTION The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs d

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ECL/PECL 9-bit Shift Register

DESCRIPTION The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs d

文件：74.84 Kbytes 页数：5 Pages

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ECL/PECL 4-Input OR/NOR

DESCRIPTION The AZ10/100EL01 is a 4-input OR/NOR gate. The device is functionally equivalent to the E101 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E101, the EL01 is ideally suited for those applications that requ

文件：73.24 Kbytes 页数：6 Pages

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ECL/PECL 4-Input OR/NOR

DESCRIPTION The AZ10/100EL01 is a 4-input OR/NOR gate. The device is functionally equivalent to the E101 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E101, the EL01 is ideally suited for those applications that requ

文件：73.24 Kbytes 页数：6 Pages

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