ECL/PECL 9-bit Shift Register

DESCRIPTION The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs d

文件：74.84 Kbytes 页数：5 Pages

AZM

9-BIT SHIFT REGISTER

Description The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 − D8 accept parallel input data, while S-IN accepts serial input data. The Qn output

文件：109.05 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

9-BIT SHIFT REGISTER

DESCRIPTION The SY10/100E142 are high-speed 9-bit shift registers designed for use in new, high-performance ECL systems. The E142 can accept serial or parallel data to be shifted out in one direction as both serial and parallel outputs. The nine inputs, D0-D8, accept parallel input data, while S-

文件：71.84 Kbytes 页数：4 Pages

MICREL

麦瑞半导体

9-BIT SHIFT REGISTER

DESCRIPTION The SY10/100E142 are high-speed 9-bit shift registers designed for use in new, high-performance ECL systems. The E142 can accept serial or parallel data to be shifted out in one direction as both serial and parallel outputs. The nine inputs, D0-D8, accept parallel input data, while S-

文件：71.84 Kbytes 页数：4 Pages

MICREL

麦瑞半导体