20G Active Retimer for USB 3.2

Features  Built-in re-timer - Integrated re-timer for USB 3.2 with two lanes up to Gen2 @ 10Gbps each for a combined 20G throughput - Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re-timer (BLR) Architectures of USB 3.2 Specification - Supports both host (source)

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10G Active Mux (1x2) with Integrated Re-timer and CC Detection for USB 3.2

Features  Built-in re-timer − Integrated re-timer for USB 3.2 up to Gen2 @ 10Gbps − Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re-timer (BLR) Architectures of USB 3.2 Specification (Appendix-E) − Loss compensation to recover up to 23dB channel loss  Integrat

文件：222.26 Kbytes 页数：2 Pages

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20G Active Mux (2x2) with Integrated Re-timer and CC Detection for USB 3.2

Features  Built-in re-timer − Integrated re-timer for USB 3.2 up to Gen 2 @ 2x10Gbps for a combined 20G data throughput − Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re-timer (BLR) Architectures of USB 3.2 Specification (Appendix-E) − Supports both host (source

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106 Active Mux (6x4) with Integrated Re-timers for USB3.2/DisplayPort1.4

Features * Built-in re-timers — Integrated re-timers for USB3.2 up to Gen 2 @ 10Gbps — Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re-timer (BLR) Architectures of USB3.2 Specification (Appendix-E) — Integrated re-timers (Link training-tunable PHY repeater) for D

文件：802.27 Kbytes 页数：2 Pages

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10G Active Mux (4x4) with Integrated Re-timers for USB3.2/DisplayPort™

Features  Built-in re-timers − Integrated re-timers for USB3.2 up to Gen 2 @ 10Gbps − US3.2 Specification (Appendix-E) compliant re-timer − Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re-timer (BLR) Architectures of USB3.2 Specification (Appendix-E) − Integrat

文件：226.23 Kbytes 页数：2 Pages

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Bidirectional Active USB-C™ Cable for USB3.2 (10G) and DP1.3 (8.1G)

Features  Bidirectional active USB-C cable carrying 4L DP or 2L DP and USB3.2 - Supports up to 4L of DisplayPort in/out, with signal conditioning up to 8.1Gbps (supports HBR3, HBR2, HBR, RBR rates) - Supports USB3.1 in/out, with signal conditioning up to 10Gbps - Supports USB2.0 (480Mbps) -

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12G Active Redriver with Linear Equalization for HDMI 2.1

Features  Built-in CTLE redrivers - Independent channel configuration - Loss compensation to recover up to -12dB channel loss @ 12Gbps  Four lanes of HDMI 2.1 up to 12Gbps - Supports DP++  Serial and debug interfaces - I2C Slave interface, up to 1MHz, for redriver configuration  Indust

文件：370.48 Kbytes 页数：2 Pages

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10G USB 3.2 Re-timer (1-Port)

Features * Built-in re-timer ㅡ Integrated re-timer for USB 3.2 1-port (Tx/Rx) up to 10Gbps ㅡ Supports both Separate Reference Clock Independent SSC (SRIS) and Bit-Level Re- * timer (BLR) Architectures of USB3.1 Specification (Appendix-E) ㅡ 1055 compensation to recover up to 23dB channel loss

文件：668.15 Kbytes 页数：2 Pages

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10G Active Redriver with Linear Equalization for USB3.2/DisplayPort™

Features • Built-in redrivers − Integrated re-driver for USB3.2 up to Gen 2 @ 10Gbps − Integrated re-drivers for DisplayPort up to UHBR10 @ 10Gbps. − Supports both host (source) and device (sink) applications in USB-C subsystems with DisplayPort Alternate Mode − Loss compensation to recover u

文件：254.72 Kbytes 页数：3 Pages

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DisplayPort 1.4 to HDMI2.0b Converter

Features  VESA DisplayPortTM (DP) v1.4 compliant receiver - 1, 2 and 4 lanes up to HBR3 (8.1Gbps) input - 1 MHz AUX Channel - Horizontal Blanking Expansion Operation - 27dB insertion loss recovery  HDMI Specification v2.0b compliant transmitter - TMDS scrambling up to 600MHz pixel clock r

文件：182.39 Kbytes 页数：2 Pages

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