ADSP-SC591中文资料Up to 800 MHz SHARC+® DSP w/ Integrated Arm® Cortex®-A5数据手册ADI规格书

描述 Description

Reaching speeds of up to 1 GHz, the ADSP-SC59x processors are members of the SHARC® family of products. The ADSP-SC59x processor is a dual-SHARC+® core DSP that doubles the audio performance of its single-SHARC+ core ADSP-2156x predecessor and adds an integrated Arm Cortex-A5 core, also running at up to 1 GHz. The A5 processor, with FPU and Neon® DSP extensions, handles additional real-time processing tasks and manages peripherals used to interface to time-critical data in audio applications. These interfaces include Gigabit Ethernet, USB High-Speed, CAN FD, and a rich variety of other connectivity options for a flexible and simplified system design.

The ADSP-SC59x SHARC processors are members of the SIMD SHARC family of digital signal processors (DSPs) that feature Analog Devices, Inc., Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a rich set of industry-leading system peripherals and memory (see Table 1 in the data sheet), the SHARC+ processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

APPLICATIONS

Automotive: audio amplifier, head unit, ANC/RNC, rear seat entertainment, digital cockpit, ADAS Consumer & Professional Audio: speakers, sound bars, AVRs, conferencing systems, mixing consoles, microphone arrays, headphones

特性 Features

SHARC+ Core Infrastructure
• 800 MHz(max) Core clock frequency
• 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance
• 32-bit, 40-bit & 64-bit floating point support
• 32-bit fixed point
• Byte, short-word, word, long-word addressed
Arm Core Infrastructure
• 800 MHz Arm Cortex-A5 (with Neon/FPU)
• 32 kByte/32 kByte L1 Instr./Data Cache
• 256 kByte L2 Cache
Memory
• 1024 KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases
• Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices)
16-bit DDR/DDR3L Memory Controller
• 1.35V support for DDR3L
Advanced Hardware Accelerators
• Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power
• Security Crypto Engines with OTP
Powerful DMA SystemInnovative Digital Audio Interface (DAI) includes:
• 8x Full SPORT interfaces w/TDM & I2S modes
• 2x S/PDIF Rx/Tx, 8 ASRC pairs
• 8x Precision Clock Generators
• 2x 4-channel PDM Mic Inputs
• 40 Buffers
Other Peripheral Connectivity / Interfaces
• 2x Quad SPI, 1x Octal SPI
• MLB 3-pin / 6-pin
• 6x I2C,3x UARTs
• 2x Link Ports
• 16x General Purpose Timer, 1x General Purpose Counter
• 3x Watchdog Timers
• ePPI
• USB 2.0 HS OTG Controller
• 10/100 EMAC
• 10/100/1000 EMAC w/AVB and 1588
• 2x CAN FD
• 8-ch 12bit Housekeeping ADC
• 135 GPIO pins, 40 DAI pins
• Thermal Sensor
Package
• 17mm x 17mm (0.8mm pitch) 400-ball FCBGA
Additional Features
• Security and Protection
• Crypto hardware accelerators
• Fast secure boot with IP protection

• Enhanced FIR and IIR accelerators running up to 1 GHz
• AEC-Q100 qualified for automotive applications