SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

文件：3.26181 Mbytes 页数：143 Pages

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Up to 800 MHz SHARC+® DSP w/ Integrated Arm® Cortex®-A5

Reaching speeds of up to 1 GHz, the ADSP-SC59x processors are members of the SHARC® family of products. The ADSP-SC59x processor is a dual-SHARC+® core DSP that doubles the audio performance of its single-SHARC+ core ADSP-2156x predecessor and adds an integrated Arm Cortex-A5 core, also running at u SHARC+ Core Infrastructure• 800 MHz(max) Core clock frequency\n• 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance\n• 32-bit, 40-bit & 64-bit floating point support\n• 32-bit fixed point\n• Byte, short-word, word, long-word addressed\nArm Core Infrastructure• 800;

ADI

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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