SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

文件：3.26181 Mbytes 页数：143 Pages

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高达 1GHz 的双 SHARC+® DSP，带有两个 640KB L1、2048KB 共享 L2 SRAM 和 400 球 FCBGA

ADSP-2159x 处理器的速度高达 1 GHz，属于 SHARC® 系列产品。ADSP-2159x 处理器是一款双 SHARC+ ®内核 DSP，其音频性能是其前代单 SHARC+ 内核 ADSP-2156x 的两倍，同时保持 BGA 封装的引脚兼容性，并具有 400 MHz (ADSP-21566) 至 2 GHz (ADSP-21593) 的设计可扩展性。\n\n ADSP-2159x SHARC 处理器是 SIMD SHARC 系列数字信号处理器 (DSP) 中的一款产品，采用 ADI 公司的超级哈佛架构。这些 32 位/40 位/64 位浮点处理器已针对高性能音频/浮点应 SHARC+ Core 基础设施\n• 800MHz（最大值）或 1 GHz（最大值） 内核时钟频率\n\n• 两个 640KB  片内 1 级 (L1) SRAM 存储器（具有奇偶校验功能）可增强低延迟性能\n\n• 32 位、40 位和 64 位浮点支持\n\n• 32 位固定点\n\n• 对字节、短字、字、长字寻址\n\n\n存储器\n• 2048 KB 片内 2 级(L2) SRAM（具有 ECC 保护功能）- 在许多用例中不再需要外部存储器\n\n• 3 级 (L3) 接口已针对低系统功耗进行优化，可为 DDR3（支持以 1.35 V 工作的 DDR3L 套件）提供 16 位接口\n;

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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