SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

文件：3.26181 Mbytes 页数：143 Pages

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高达1 GHz的双核SHARC+® DSP（带2个640KB L1）、2048KB共用的L2 SRAM

ADSP-2159x处理器运行速度可达1 GHz，属于SHARC®系列产品。ADSP-2159x处理器是一款双核SHARC+® DSP，其音频性能为单核SHARC+ ADSP-2156x产品的两倍。\n\n ADSP-2159x SHARC处理器属于SIMD SHARC系列数字信号处理器(DSP)，采用ADI公司的Super Harvard架构。这些32/40/64位浮点处理器针对高性能音频/浮点应用进行了优化，具有大容量片内静态随机存取存储器(SRAM)，可消除输入/输出(I/O)瓶颈的多条内部总线，并且提供创新的数字音频接口(DAI)。SHARC+内核最新加入的特性包括缓存增强和 SHARC+内核基础架构 \n• 2个640KB 片内1级(L1) SRAM存储器（支持奇偶校验）提高了低延迟性能\n• 支持32、40和64位浮点\n• 32位定点\n• 字节、短字、字、长字寻址\n• 2048 KB 片内2级(L2) SRAM，具有ECC保护功能，在许多用例中无需外部存储器\n• 针对低系统功耗而优化的3级(L3)接口，提供与DDR3（支持1.35 V DDR3L器件）相连的16位接口\n• DDR3L支持1.35V\n• 增强型FIR/IIR加速引擎以内核时钟频率运行，可提高处理能力\n• 带OTP的安全加密引擎\n\n\n强大的DMA系统;

ADI

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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