SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

文件：3.26181 Mbytes 页数：143 Pages

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800 MHz双核SHARC+® DSP（带2个640KB L1）、1024KB共用的L2 SRAM、400引脚FCBGA封装

ADSP-2159x处理器运行速度可达1 GHz，属于SHARC®系列产品。ADSP-2159x处理器是一款双核SHARC+® DSP，其音频性能为前代单核SHARC+ ADSP-2156x产品的两倍，同时在BGA封装中与其引脚兼容，提供400 MHz (ADSP-21566)至2 GHz (ADSP-21593)的设计可扩展性。\n\n ADSP-2159x SHARC处理器属于SIMD SHARC系列数字信号处理器(DSP)，采用ADI公司的Super Harvard架构。这些32/40/64位浮点处理器针对高性能音频/浮点应用进行了优化，具有大容量片内静态随机存取存储器(SRA SHARC+内核基础架构 • 800 MHz（最大值） 内核时钟频率\n• 支持32、40和64位浮点\n• 字节、短字、字、长字寻址\n• 1024 KB 片内2级(L2) SRAM，具有ECC保护功能，在许多用例中无需外部存储器\n• DDR3L支持1.35V\n• 增强型FIR/IIR加速引擎以内核时钟频率运行，可提高处理能力\n• 8个全SPORT接口（提供TDM和I2S模式）\n• 8个精密时钟发生器\n• 28个缓冲器\n• 2个四通道SPI、1个八通道SPI\n• 6个I2C、3个UART\n• 16个通用定时器、1个通用计数器\n• 4通道12位管理ADC\n• 热传感器\n•;

ADI

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

文件：3.26181 Mbytes 页数：143 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

文件：3.26181 Mbytes 页数：143 Pages

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