ADC12DJ800

具有 JESD204C 接口的双通道 12 位 800MSPS 模数转换器 (ADC); • ADC Core: \n• Resolution: 12 Bit\n• Maximum sampling rate: 800 MSPS\n• Non-interleaved architecture\n• Internal dither reduces high-order harmonics\n \n• Performance specifications (–1 dBFS): \n• SNR (97 MHz): 57.6 dBFS\n• ENOB (97 MHz): 9.0 Bits\n• SFDR (97 MHz): 62 dBFS\n• Noise floor (–20 dBFS): –146.1 dBFS/Hz\n \n• Full-scale input voltage: 800 mVPP-DIFF \n• Full-power input bandwidth: 6 GHz\n• JESD204C Serial data interface: \n• Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes\n• Maximum baud-rate: 17.16 Gbps\n• 64B/66B and 8B/10B encoding modes\n• Subclass-1 support for deterministic latency\n• Compatible with JESD204B receivers\n \n• Optional internal sampling clock generation \n• Internal PLL and VCO (7.2–8.2 GHz)\n \n• SYSREF Windowing eases synchronization\n• Four clock outputs simplify system clocking \n• Reference clocks for FPGA or adjacent ADC\n• Reference clock for SerDes transceivers\n \n• Timestamp input and output for pulsed systems\n• Power consumption (800 MSPS): \n• Quad Channel: 415 mW / channel\n• Dual channel: 555 mW / channel\n• Single channel: 830 mW\n \n• Power supplies: 1.1 V, 1.9 V;

ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems.\n\nFull-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of of L-band and S-band.

ADC12DJ800

ADC12xJ800 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface

ADC12DJ800-Q1

具有 JESD204C 接口的汽车类双通道 12 位 800MSPS 模数转换器 (ADC); • AEC-Q100 qualified for automotive applications: \n• Temperature grade 1: –40°C to +125°C, TA \n \n• ADC Core: \n• Resolution: 12 Bit\n• Maximum sampling rate: 800 MSPS\n• Non-interleaved architecture\n• Internal dither reduces high-order harmonics\n \n• Performance specifications (–1 dBFS): \n• SNR (97 MHz): 57.6 dBFS\n• ENOB (97 MHz): 9.0 Bits\n• SFDR (97 MHz): 62 dBFS\n• Noise floor (–20 dBFS): –146.1 dBFS/Hz\n \n• Full-scale input voltage: 800 mVPP-DIFF \n• Full-power input bandwidth: 6 GHz\n• JESD204C Serial data interface: \n• Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes\n• Maximum baud-rate: 17.16 Gbps\n• 64B/66B and 8B/10B encoding modes\n• Subclass-1 support for deterministic latency\n• Compatible with JESD204B receivers\n \n• Optional internal sampling clock generation \n• Internal PLL and VCO (7.2–8.2 GHz)\n \n• SYSREF Windowing eases synchronization\n• Four clock outputs simplify system clocking \n• Reference clocks for FPGA or adjacent ADC\n• Reference clock for SerDes transceivers\n \n• Timestamp input and output for pulsed systems\n• Power consumption (800 MSPS): \n• Quad Channel: 415 mW / channel\n• Dual channel: 555 mW / channel\n• Single channel: 830 mW\n \n• Power supplies: 1.1 V, 1.9 V;

ADC12xJ800-Q1 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC12xJ800-Q1 is qualified for automotive applications.\n\nFull-power input bandwidth (-3 dB) of 6 GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band.

ADC12DJ800AAV

丝印：ADC12DJ800；Package：FCBGA；ADC12xJ800 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface

ADC12DJ800AAVQ1

丝印：ADC12DJ800Q1；Package：FCBGA；ADC12xJ800-Q1 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface

ADC12DJ800AAVT

丝印：ADC12DJ800；Package：FCBGA；ADC12xJ800 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface

ADC12DJ800AAVTQ1

丝印：ADC12DJ800Q1；Package：FCBGA；ADC12xJ800-Q1 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface

ADC12DJ800-Q1

ADC12xJ800-Q1 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface

ADC12DJ800-Q1

ADC12xJ800 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface