Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 页数：16 Pages

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双路输出网络时钟发生器

AD9575是一款高度集成的双路输出时钟发生器，包括一个针对网络定时而优化的片内PLL内核。整数N分频PLL设计基于ADI公司成熟的高性能、低抖动频率合成器系列，可实现线路卡的较高性能。对相位噪声和抖动要求苛刻的其它应用也能受益于该器件。          PLL部分由低噪声鉴频鉴相器(PFD)、精密电荷泵、低相位噪声压控振荡器(VCO)和引脚可选的反馈与输出分频器组成。通过连接一个外部晶振，可以将常用的网络输出频率锁定至输入参考。输出分频比和反馈分频比可针对所要求的输出速率，通过引脚进行编程。无需外部环路滤波器，从而节省宝贵的设计时间和电路板空间。\n\n   AD957 • 完全集成的VCO/PLL内核\n\n• 均方根抖动：0.39 ps（12 kHz至20 MHz，156.25 MHz）\n\n• 均方根抖动：0.15 ps（1.875 MHz至20 MHz，156.25 MHz）\n\n• 均方根抖动：0.40 ps（12 kHz至20 MHz，106.25 MHz）\n\n• 均方根抖动：0.15 ps（637 kHz至10 MHz，106.25 MHz）;

ADI

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Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 页数：16 Pages

AD

亚德诺

Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 页数：16 Pages

AD

亚德诺

Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 页数：16 Pages

AD

亚德诺

Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 页数：16 Pages

AD

亚德诺

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：托盘 类别：集成电路（IC） 应用特定时钟/定时 描述：IC PLL CLOCK GEN 25MHZ 16TSSOP

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亚德诺

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：托盘 类别：集成电路（IC） 应用特定时钟/定时 描述：IC PLL CLOCK GEN 25MHZ 16TSSOP

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