Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 页数：16 Pages

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亚德诺

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：托盘 类别：集成电路（IC） 应用特定时钟/定时 描述：IC PLL CLOCK GEN 25MHZ 16TSSOP

AD

亚德诺

Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 页数：16 Pages

AD

亚德诺

Network Clock Generator, Two Outputs

GENERAL DESCRIPTION The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthes

文件：316.94 Kbytes 页数：16 Pages

AD

亚德诺

P-Channel 60-V (D-S) MOSFET

文件：988.33 Kbytes 页数：8 Pages

VBSEMI

微碧半导体