Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

文件：672.93 Kbytes 页数：44 Pages

AD

亚德诺

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes 页数：44 Pages

AD

亚德诺

带双路PLL、扩频和余量微调功能的时钟发生器

AD9577既提供一个多路输出时钟发生器功能，又带有两个片上锁相环内核PLL1和PLL2，专门针对网络时钟应用而优化。PLL设计基于ADI公司成熟的高性能、低抖动频率合成器产品系列，确保实现较高的网络性能。PLL具有I2C 可编程输出频率和格式。小数N分频PLL可支持扩频时钟功能，降低EMI辐射的峰值功率。两个PLL均可支持频率余量微调功能。 第一个整数N分频PLL部分(PLL1)由一个鉴频鉴相器(PFD)、一个电荷泵(CP)、一个低噪声电压控制振荡器(VCO)、一个可编程反馈分频器和两个独立可编程输出分频器组成。通过将外部晶振或基准时钟连接至REFCLK引脚，可将最高达637.5 • 完全集成双路PLL/VCO内核 \n\n• 1个整数N分频和1个小数N分频PLL \n\n• 连续频率范围：11.2 MHz至200 MHz\n-- 提供200 MHz至637.5 MHz的大多数频率\n\n• PLL1相位抖动\n（12 kHz至20 MHz）:\n460 fs rms（典型值）\n\n• PLL2相位抖动（12 kHz至20 MHz）\n- 整数N分频模式:470 fs rms（典型值）\n- 小数N分频模式:660 fs rms（典型值）;

ADI

亚德诺

Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

文件：672.93 Kbytes 页数：44 Pages

AD

亚德诺

Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

文件：672.93 Kbytes 页数：44 Pages

AD

亚德诺

Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

文件：672.93 Kbytes 页数：44 Pages

AD

亚德诺

Clock Generator with Dual PLLs

GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequ

文件：672.93 Kbytes 页数：44 Pages

AD

亚德诺

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes 页数：44 Pages

AD

亚德诺

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes 页数：44 Pages

AD

亚德诺

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

文件：746.39 Kbytes 页数：44 Pages

AD

亚德诺