1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz differ

文件：656.95 Kbytes 页数：28 Pages

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1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are two independe

文件：407.42 Kbytes 页数：28 Pages

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Low Jitter Sampling Clock Generator for High Performance ADCs

文件：121.28 Kbytes 页数：3 Pages

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1.6 GHz时钟分配IC，分频器，延迟调整，两路输出

AD9515是一款两路输出时钟分配IC，具有低抖动和低相位噪声特性，有助于实现优质数据转换器性能。这款器件也适合相位噪声和抖动要求严格的其它应用。\n\n 它提供两路独立的时钟输出，一路输出为LVPECL，另一路输出可以设置为LVDS或CMOS电平。LVPECL输出工作频率为1.6 GHz。另一路输出在LVDS模式下的工作频率为800 MHz，在CMOS模式下的工作频率为250 MHz。\n\n 每路输出都具有可编程分频器，可设置1至32的整数分频比。一路时钟输出相对于其它时钟输出的相位可通过分频器相位选择功能进行设置，用作时序粗调。\n\n LVDS/CMOS输 • 1.6 GHz 差分时钟输入 \n\n• 2 个可编程分频器，编程范围：\n1 至32 \n用于输出到输出延迟粗调的相位选择 \n\n• 1.6 GHz LVPECL 时钟输出\nLVPECL加性输出均方根抖动：225 fs;

ADI

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1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz differ

文件：656.95 Kbytes 页数：28 Pages

AD

亚德诺

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are two independe

文件：407.42 Kbytes 页数：28 Pages

AD

亚德诺

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are two independe

文件：407.42 Kbytes 页数：28 Pages

AD

亚德诺

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are two independe

文件：407.42 Kbytes 页数：28 Pages

AD

亚德诺

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz differ

文件：656.95 Kbytes 页数：28 Pages

AD

亚德诺

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

GENERAL DESCRIPTION The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. FEATURES 1.6 GHz differ

文件：656.95 Kbytes 页数：28 Pages

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