AD9515/PCBZ开发板套件编程器的评估演示板及套件规格书PDF中文资料

AD9515/PCBZ属于开发板套件编程器的评估演示板及套件。由亚德诺半导体技术有限公司制造生产的AD9515/PCBZ评估和演示板及套件该系列产品提供了一种方便的方法，在经过验证的实施环境中评估某些重点器件的性能或特性。评估方法通常有完善的文档说明，并且视乎具体情况由评估软件提供支持。产品通常由印刷电路板组成，板上已装有重点器件以及必要或有用的支持元器件，另外也可能包括其他组件，例如电缆或电源。对于数量特别多或类别独特的器件类别(如 ADC、DAC 和开关模式电源)，评估平台可组合为一个单独的产品系列。

GENERAL DESCRIPTION

The AD9515 features a two-output clock distribution IC in a

design that emphasizes low jitter and phase noise to maximize

data converter performance. Other applications with

demanding phase noise and jitter requirements also benefit

from this part.

There are two independent clock outputs. One output is

LVPECL, while the other output can be set to either LVDS or

CMOS levels. The LVPECL output operates to 1.6 GHz. The

other output operates to 800 MHz in LVDS mode and to

250 MHz in CMOS mode.

Each output has a programmable divider that can be set to

divide by a selected set of integers ranging from 1 to 32. The

phase of one clock output relative to the other clock output can

be set by means of a divider phase select function that serves as

a coarse timing adjustment.

The LVDS/CMOS output features a delay element with three

selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each

with 16 steps of fine adjustment.

The AD9515 does not require an external controller for

operation or setup. The device is programmed by means of

11 pins (S0 to S10) using 4-level logic. The programming pins

are internally biased to ⅓ VS. The VREF pin provides a level of

⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.

The AD9515 is ideally suited for data converter clocking

applications where maximum converter performance is

achieved by encode signals with subpicosecond jitter.

The AD9515 is available in a 32-lead LFCSP and operates from

a single 3.3 V supply. The temperature range is −40°C to +85°C.

FEATURES

1.6 GHz differential clock input

2 programmable dividers

Divide-by in range from1 to 32

Phase select for coarse delay adjust

1.6 GHz LVPECL clock output

Additive output jitter 225 fs rms

800 MHz/250 MHz LVDS/CMOS clock output

Additive output jitter 300 fs rms/290 fs rms

Time delays up to 10 ns

Device configured with 4-level logic pins

Space-saving, 32-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

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