1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

GENERAL DESCRIPTION The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential c

文件：838.3 Kbytes 页数：40 Pages

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1.65 GHz Clock Fanout Buffer

文件：1.0097 Mbytes 页数：40 Pages

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1.65 GHz时钟扇出缓冲器，集成输出分频器和延迟调整

AD9508提供时钟扇出能力，针对能使系统性能达到优质的低抖动进行设计。这款器件能满足时钟数据转换器等应用所需的相位噪声和低抖动要求，可优化这些应用的性能。\n\n 它集成4个独立的差分时钟输出，每一个输出都支持多种逻辑电平类型。包括LVDS (1.65 GHz)、HSTL (1.65 GHz)和1.8 V CMOS (250 MHz)。在1.8 V CMOS输出模式下，差分输出转换为两个CMOS单端信号。无论工作电源电压如何改变，CMOS输出始终为1.8 V逻辑电平。 \n\n 每路输出都有一个可编程分频器，可以旁路该分频器或者设置最高1024的整数分频比。此外，AD95 • 1.65 GHz差分时钟输入/输出 \n\n• 10位可编程分频器，1至1024整数分频比 \n\n• 高达4个差分输出或8个CMOS输出 \n\n• 用于上电时进行硬连线编程的引脚绑定功能\n\n• 宽带随机抖动：<115 fs rms \n\n• 加性输出抖动：41fs rms（12 KHz至20 MHz） \n\n• 出色的输出间隔离\n\n• 所有输出自动同步\n\n• 欲了解更多特性，请参考数据手册;

ADI

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1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

GENERAL DESCRIPTION The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential c

文件：838.3 Kbytes 页数：40 Pages

AD

亚德诺

1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

GENERAL DESCRIPTION The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential c

文件：838.3 Kbytes 页数：40 Pages

AD

亚德诺

1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

GENERAL DESCRIPTION The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential c

文件：838.3 Kbytes 页数：40 Pages

AD

亚德诺

1.65 GHz Clock Fanout Buffer

文件：1.0097 Mbytes 页数：40 Pages

AD

亚德诺

1.65 GHz Clock Fanout Buffer

文件：1.0097 Mbytes 页数：40 Pages

AD

亚德诺

1.65 GHz Clock Fanout Buffer

文件：1.0097 Mbytes 页数：40 Pages

AD

亚德诺

Package：24-WFQFN 裸露焊盘，CSP；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：IC CLK BUFF 1:4 1.65GHZ 24LFCSP

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