丝印：ACT11；Package：SOIC；SNx4ACT11 Triple 3-Input AND Gates

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 10.5ns at 5V • Inputs are TTL-voltage compatible 2 Description The SNx4ACT11 device contains three independent 3-input AND gates. These devices perform the Boolean function Y = A • B • C in positive log

文件：2.65663 Mbytes 页数：36 Pages

TI

德州仪器

丝印：ACT11；Package：SOIC；SNx4ACT11 Triple 3-Input AND Gates

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 10.5ns at 5V • Inputs are TTL-voltage compatible 2 Description The SNx4ACT11 device contains three independent 3-input AND gates. These devices perform the Boolean function Y = A • B • C in positive log

文件：2.65663 Mbytes 页数：36 Pages

TI

德州仪器

丝印：ACT11；Package：SOIC；SNx4ACT11 Triple 3-Input AND Gates

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 10.5ns at 5V • Inputs are TTL-voltage compatible 2 Description The SNx4ACT11 device contains three independent 3-input AND gates. These devices perform the Boolean function Y = A • B • C in positive log

文件：2.65663 Mbytes 页数：36 Pages

TI

德州仪器

丝印：ACT11004；Package：SOIC；HEX INVERTER

Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Smal

文件：698.4 Kbytes 页数：15 Pages

TI

德州仪器

丝印：ACT11008；Package：SOIC；QUADRUPLE 2-INPUT POSITIVE-AND GATE

Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICE (Enhanced-Performance Implanted CMOS) 1-
m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D), Plastic Thin Shrink Small-Outli

文件：429.54 Kbytes 页数：13 Pages

TI

德州仪器

丝印：ACT11008；Package：SOIC；QUADRUPLE 2-INPUT POSITIVE-AND GATE

Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICE (Enhanced-Performance Implanted CMOS) 1-
m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D), Plastic Thin Shrink Small-Outli

文件：429.54 Kbytes 页数：13 Pages

TI

德州仪器

丝印：ACT11032；Package：SOIC；QUADRUPLE 2-INPUT POSITIVE-OR GATES

Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-
m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages (D), Plastic Shrink Small

文件：326.91 Kbytes 页数：12 Pages

TI

德州仪器

丝印：ACT11032；Package：SOIC；QUADRUPLE 2-INPUT POSITIVE-OR GATES

Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-
m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages (D), Plastic Shrink Small

文件：326.91 Kbytes 页数：12 Pages

TI

德州仪器

丝印：ACT11032；Package：SOIC；QUADRUPLE 2-INPUT POSITIVE-OR GATES

Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-
m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages (D), Plastic Shrink Small

文件：326.91 Kbytes 页数：12 Pages

TI

德州仪器

丝印：ACT11074；Package：SOIC；DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-
m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB)

文件：664.34 Kbytes 页数：18 Pages

TI

德州仪器