丝印：ABTH16823；Package：SSOP；18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Typical VOLP (Output Ground Bounce)

文件：570.28 Kbytes 页数：13 Pages

TI

德州仪器

丝印：ABTH16823；Package：SSOP；18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Typical VOLP (Output Ground Bounce)

文件：570.28 Kbytes 页数：13 Pages

TI

德州仪器

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumpt

文件：103.3 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumpt

文件：103.3 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：99.78 Kbytes 页数：12 Pages

PHI

PHI