15-Output DB1900Z Derivative for PCIe Gen1?? and UPI

文件：292.79 Kbytes 页数：23 Pages

IDT

15 to 19-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ LP-HCSL outputs eliminate up to 4 resistors per output pair ▪ 9 selectable SMBus addresses ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies ▪ Hardware/SMBus control of ZDB and FOB modes allow change without power cycle ▪ 8 OE# pins support PCIe CLKR

文件：1.05564 Mbytes 页数：35 Pages

RENESAS

瑞萨

15 to 19-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ LP-HCSL outputs eliminate up to 4 resistors per output pair ▪ 9 selectable SMBus addresses ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies ▪ Hardware/SMBus control of ZDB and FOB modes allow change without power cycle ▪ 8 OE# pins support PCIe CLKR

文件：1.05564 Mbytes 页数：35 Pages

RENESAS

瑞萨

15-Output DB1900Z Derivative for PCIe Gen1?? and UPI

文件：292.79 Kbytes 页数：23 Pages

IDT

15-Output DB1900Z Derivative for PCIe Gen1?? and UPI

文件：292.79 Kbytes 页数：23 Pages

IDT

15-Output DB1900ZL PCIe Zero-Delay/Fanout Clock Buffer

The 9ZXL1530D is a second-generation enhanced-performance DB1900Z-derivative differential buffer. The part is a pin-compatible upgrade to the 9ZXL1530B, while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications. • LP-HCSL outputs; eliminate 30 resistors, save 51mm² of area\n• PCIe Gen 1–5 compliance\n• SMBus OE bits; software control of each output\n• 9 selectable SMBus addresses; multiple devices can share the same SMBus segment\n• Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies\n• H;

Renesas

瑞萨

Package：64-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：DB1500ZL OEM DERIV

Renesas Electronics America Inc

Package：64-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：DB1500ZL OEM DERIV

Renesas Electronics America Inc