12-Output DB1200ZL Derivative for PCIe Gen1?? and UPI

文件：254.62 Kbytes 页数：21 Pages

IDT

6 to 12-Output Buffers for PCIe Gen1–5 and UPI with SMBus Write Protect

Features ▪ SMBus Write Protect pin prevents SMBus against accidental writes ▪ 6–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selec

文件：1.27342 Mbytes 页数：32 Pages

RENESAS

瑞萨

6 to 12-Output Buffers for PCIe Gen1–5 and UPI with SMBus Write Protect

Features ▪ SMBus Write Protect pin prevents SMBus against accidental writes ▪ 6–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selec

文件：1.27342 Mbytes 页数：32 Pages

RENESAS

瑞萨

12-Output DB1200ZL Derivative for PCIe Gen1?? and UPI

文件：254.62 Kbytes 页数：21 Pages

IDT

12-Output DB1200ZL Derivative for PCIe Gen1?? and UPI

文件：254.62 Kbytes 页数：21 Pages

IDT

12-Output DB1200ZL PCIe Zero-Delay/Fanout Clock Buffer with SMBus Write Protection

The 9ZXL1232E is a second-generation, enhanced-performance DB1200ZL differential buffer. The part is a\n\npin-compatible upgrade to the 9ZXL1232A, while offering a much improved phase jitter performance and an SMBus Write Lock feature for increased system security. A fixed external feedback maintain SMBus write lock feature; increases system security\nPCIe Gen 1–5 compliance\nLP-HCSL outputs; eliminate 24 resistors, save 41mm² of area\n12 OE# pins; hardware control of each output\n9 selectable SMBus addresses; multiple devices can share the same SMBus segment\nSelectable PLL BW; minimizes jitte;

Renesas

瑞萨

Package：64-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：DB1200ZL OEM DERIVATIVE + WRTLK

Renesas Electronics America Inc

Package：64-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：DB1200ZL OEM DERIVATIVE + WRTLK

Renesas Electronics America Inc