8-Output DB800ZL Derivative PCIe Gen1?? and UPI

文件：274.17 Kbytes 页数：18 Pages

IDT

6 to 12-Output Buffers for PCIe Gen1–5 and UPI with SMBus Write Protect

Features ▪ SMBus Write Protect pin prevents SMBus against accidental writes ▪ 6–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selec

文件：1.27342 Mbytes 页数：32 Pages

RENESAS

瑞萨

6 to 12-Output Buffers for PCIe Gen1–5 and UPI with SMBus Write Protect

Features ▪ SMBus Write Protect pin prevents SMBus against accidental writes ▪ 6–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selec

文件：1.27342 Mbytes 页数：32 Pages

RENESAS

瑞萨

8-Output DB800ZL Derivative PCIe Gen1?? and UPI

文件：274.17 Kbytes 页数：18 Pages

IDT

8-Output DB800ZL Derivative PCIe Gen1?? and UPI

文件：274.17 Kbytes 页数：18 Pages

IDT

8-Output DB800ZL PCIe PCIe Zero-Delay/Fanout Clock Buffer with SMBus Write Protection

The 9ZXL0832E is a second-generation, enhanced performance DB800ZL differential buffer. The part is pin-compatible to the 9ZXL0831A while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL0832E has an SMBus Wri • SMBus write lock feature; increases system security\n• PCIe Gen 1–5 compliance\n• LP-HCSL outputs; eliminate 16 resistors, save 27mm² of area\n• 8 OE# pins; hardware control of each output\n• Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies\n• Hardware/SMBus control of PLL ba;

Renesas

瑞萨

Package：48-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：DB800ZL OEM DERIVATIVE + WRTLK

Renesas Electronics America Inc

Package：48-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：DB800ZL OEM DERIVATIVE + WRTLK

Renesas Electronics America Inc