8-OUTPUT DB800ZL

Features/Benefits • Low-power push-pull outputs; Save power and board space - no Rp • Space-saving 48-pin VFQFPN package • Fixed feedback path for 0ps input-to-output delay • 8 OE# pins; hardware control of each output • PLL or bypass mode; PLL can dejitter incoming clock • 100MHz or 133MHz

文件：555.74 Kbytes 页数：19 Pages

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Low-power push-pull outputs

文件：349.96 Kbytes 页数：18 Pages

IDT

8-OUTPUT

文件：347.54 Kbytes 页数：18 Pages

IDT

8-Output Low-power Buffer for PCIe Gen1/2/3 and QPI/UPI

The 9ZXL0831 is a low-power 8-output differential buffer that meets all the performance requirements of the Intel DB800ZL specification. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications. • 8 - 0.7V low-power HCSL-compatible output pairs\n• Space-saving 48-pin VFQFPN package \n• 8 OE# pins; hardware control of each output\n• 100MHz or 133MHz PLL mode operation; supports PCIe and QPI applications\n• Spread Spectrum Compatible; tracks spreading input clock for low EMI\n• Output-to-outp;

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瑞萨

8-OUTPUT DB800ZL

Features/Benefits • Low-power push-pull outputs; Save power and board space - no Rp • Space-saving 48-pin VFQFPN package • Fixed feedback path for 0ps input-to-output delay • 8 OE# pins; hardware control of each output • PLL or bypass mode; PLL can dejitter incoming clock • 100MHz or 133MHz

文件：555.74 Kbytes 页数：19 Pages

RENESAS

瑞萨

8-OUTPUT DB800ZL

Features/Benefits • Low-power push-pull outputs; Save power and board space - no Rp • Space-saving 48-pin VFQFPN package • Fixed feedback path for 0ps input-to-output delay • 8 OE# pins; hardware control of each output • PLL or bypass mode; PLL can dejitter incoming clock • 100MHz or 133MHz

文件：555.74 Kbytes 页数：19 Pages

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瑞萨

4 to 12-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ 4–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topolo

文件：1.35602 Mbytes 页数：34 Pages

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瑞萨

4 to 12-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ 4–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topolo

文件：1.35602 Mbytes 页数：34 Pages

RENESAS

瑞萨

4 to 12-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ 4–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topolo

文件：1.35602 Mbytes 页数：34 Pages

RENESAS

瑞萨

4 to 12-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ 4–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topolo

文件：1.35602 Mbytes 页数：34 Pages

RENESAS

瑞萨