6-Output DB800ZL Derivat ive for PCIe Gen1?? and UPI

文件：302.44 Kbytes 页数：20 Pages

IDT

6 to 12-Output Buffers for PCIe Gen1–5 and UPI with SMBus Write Protect

Features ▪ SMBus Write Protect pin prevents SMBus against accidental writes ▪ 6–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selec

文件：1.27342 Mbytes 页数：32 Pages

RENESAS

瑞萨

6 to 12-Output Buffers for PCIe Gen1–5 and UPI with SMBus Write Protect

Features ▪ SMBus Write Protect pin prevents SMBus against accidental writes ▪ 6–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selec

文件：1.27342 Mbytes 页数：32 Pages

RENESAS

瑞萨

6-Output DB800ZL Derivat ive for PCIe Gen1?? and UPI

文件：302.44 Kbytes 页数：20 Pages

IDT

6-Output DB800ZL Derivat ive for PCIe Gen1?? and UPI

文件：302.44 Kbytes 页数：20 Pages

IDT

6-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer with SMBus Write Protection

The 9ZXL0652E is a second-generation, enhanced-performance DB800ZL differential buffer. The part is functionally compatible to the 9ZXL0652A, while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL0652E has an • SMBus write lock feature; increases system security\n• LP-HCSL outputs with 85Ω Zout; eliminate 24 resistors, save 48mm² of area\n• Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies\n• Spread spectrum compatible; tracks spreading input clock for EMI reduction\n• 5 × 5 mm 40-VF;

Renesas

瑞萨

Package：40-VFQFN 裸露焊盘；包装：管件 类别：集成电路（IC） 应用特定时钟/定时 描述：DB600ZL OEM DERIV \

Renesas Electronics America Inc

Package：40-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：DB600ZL OEM DERIV \

Renesas Electronics America Inc