Programmable Slew rate for each output

Description The 9FGV0441 is an 4-output very low power clock generator for PCIe Gen 1, 2, 3 and 4 applications with integrated output terminations providing Zo = 100. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

文件：230.97 Kbytes 页数：15 Pages

IDT

4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable slew rate

文件：688.57 Kbytes 页数：17 Pages

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瑞萨

4-output 1.8V PCIe Gen1-4 Clock Generator with Zo = 100 ohms

The 9FGV0441 is an 4-output very low power clock generator for PCIe Gen1–4 applications with integrated output terminations providing Zo = 100Ω. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off. Integrated terminations provide 100Ω differential Zo; reduced component count and board space\n1.8V operation; reduced power consumption\nOE# pins; support DIF power management\nLP-HCSL differential clock outputs; reduced power and board space\nProgrammable slew rate for each output; allows tuning f;

Renesas

瑞萨

丝印：ICSV0441AIL；Package：32-VFQFPN；4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable slew rate

文件：688.57 Kbytes 页数：17 Pages

RENESAS

瑞萨

丝印：ICSV0441AIL；Package：32-VFQFPN；4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable slew rate

文件：688.57 Kbytes 页数：17 Pages

RENESAS

瑞萨

丝印：ICSV0441AIL；Package：32-VFQFPN；4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable slew rate

文件：688.57 Kbytes 页数：17 Pages

RENESAS

瑞萨

丝印：ICSV0441AIL；Package：32-VFQFPN；4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable slew rate

文件：688.57 Kbytes 页数：17 Pages

RENESAS

瑞萨

4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

文件：294.55 Kbytes 页数：16 Pages

IDT

4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

文件：294.55 Kbytes 页数：16 Pages

IDT

4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

文件：294.55 Kbytes 页数：16 Pages

IDT