2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 33Ohms

Description The 9DBV0231 is a member of Renesas’ 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management. Features/Benefits • LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs • 35mW typical power consumption in PLL mode; reduced ther

文件：750.89 Kbytes 页数：17 Pages

RENESAS

瑞萨

slew rate for each output

文件：306.89 Kbytes 页数：17 Pages

ICST

SMBus-selectable features

文件：306.89 Kbytes 页数：17 Pages

IDT

2-output 1.8V PCIe Gen1/2/3 Zero Delay /Fanout Buffer

文件：269.15 Kbytes 页数：17 Pages

IDT

2-output 1.8V PCIe Zero-Delay/Fanout Clock Buffer

The 9DBV0231 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family.  The device has 2 output enables for clock management. LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs\n35mW typical power consumption in PLL mode; minimal power consumption\nSpread Spectrum (SS) compatible; allows use of SS for EMI reduction\nOE# pins; support DIF power management\nHCSL compatible differential input; can be driven b;

Renesas

瑞萨

2-output 1.8V PCIe Gen1/2/3 Zero Delay /Fanout Buffer

文件：269.15 Kbytes 页数：17 Pages

IDT

2-output 1.8V PCIe Gen1/2/3 Zero Delay /Fanout Buffer

文件：269.15 Kbytes 页数：17 Pages

IDT

2-output 1.8V PCIe Gen1/2/3 Zero Delay /Fanout Buffer

文件：269.15 Kbytes 页数：17 Pages

IDT

2-output 1.8V PCIe Gen1/2/3 Zero Delay /Fanout Buffer

文件：269.15 Kbytes 页数：17 Pages

IDT

2-output 1.8V PCIe Gen1/2/3 Zero Delay /Fanout Buffer

文件：269.15 Kbytes 页数：17 Pages

IDT