9DBU0531数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The 9DBU0531 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. The device has 5 output enables for clock management, and 3 selectable SMBus addresses.

特性 Features

LP-HCSL outputs; save 10 resistors compared to standard HCSL outputs
35 mW typical power consumption; minimal power consumption
OE# pin for each output; support DIF power management
HCSL differential input; can be driven by common clock sources
Spread spectrum tolerant; allows reduction of EMI
Programmable slew rate for each output; allows tuning for various line lengths
Programmable output amplitude; allows tuning for various application environments
1 MHz to 167 MHz operating frequency
3.3 V tolerant SMBus interface  works with legacy controllers
Selectable SMBus addresses; multiple devices can easily share an SMBus segment
Device contains default configuration; SMBus interface not required for device operation
Space-saving 5x5 mm 32-pin VFQFPN; minimal board space