9DBL0851中文资料8-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer数据手册Renesas规格书

描述 Description

The 9DBL0851 8-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0851 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.

For information regarding evaluation boards and material, please contact your local sales representative.

特性 Features

• Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)
• PCIe Gen5 CC jitter < 150fs RMS (High-BW ZDB Mode)
• 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair
• Direct connection to 85Ω transmission lines
• Dedicated OE# pin for each output
• Spread Spectrum tolerant
• Pin or SMBus configuration
• 3 selectable SMBus addresses
• SMBus interface not required for device operation
• Easy AC-coupling to other logic families, see application note AN-891.
• Space saving 48-pin 6 × 6 mm VFQFPN

应用 Application

• 有线基础设施计算