9DB436中文资料4-Output 3.3V HCSL PCIe Buffer数据手册Renesas规格书

描述 Description

The 9DB436 is a zero delay/fanout buffer for PCI Express™ clocking. It supports PCIe Gen1–3 in zero delay mode and PCIe Gen1–4 in fanout mode. The 9DB436 also features a Safe Power Sequence (SPS) clock input. The 9DB436 is a pin-compatible upgrade to the 9DB433 and 9DB434.

特性 Features

Four 0.7V current-mode differential HCSL output pairs
PCIe Gen3 jitter < 0.6ps rms in ZDB mode
PCIe Gen4 additive jitter < 0.1ps rms in fanout mode
SPS internal receiver bias network keeps input clock parked when input is floating
Supports both 85Ω and 100Ω output impedance with appropriate resistor selection
OE# pins default to controlling outputs
Supports zero delay buffer mode and fanout mode
Selectable PLL bandwidth; minimizes jitter peaking in downstream PLL's
Spread spectrum compatible
Three selectable SMBus addresses