9DB1233数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking.

特性 Features

12 - 0.7 V current mode differential HCSL output pairs
3 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment
12 OE# pins/Hardware control of each output
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
Spread Spectrum Compatible/tracks spreading input clock for low EMI
SMBus Interface/unused outputs can be disabled
Supports undriven differential outputs in Power Down mode for power management
Output cycle-cycle jitter < 50 ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0 ps RMS
Pin compatible with DB1200 Yellow Cover Device