9DBL0641数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The 9DBL0641 6-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0641 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.

特性 Features

• Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)
• PCIe Gen5 CC jitter < 150fs RMS (High-BW ZDB Mode)
• 6 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair
• Direct connection to 100Ω transmission lines
• Dedicated OE# pin for each output
• Spread Spectrum tolerant
• Pin or SMBus configuration
• 3 selectable SMBus addresses
• SMBus interface not required for device operation
• Easy AC-coupling to other logic families, see application note AN-891.
• Space saving 40-pin 5 × 5 mm VFQFPN