9DBL0651中文资料6-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer数据手册Renesas规格书

描述 Description

The 9DBL0651 6-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0651 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.

For information regarding evaluation boards and material, please contact your local sales representative.

特性 Features

• Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)
• 6 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair
• Dedicated OE# pin for each output
• Pin or SMBus configuration
• SMBus interface not required for device operation
• Space saving 40-pin 5 × 5mm VFQFPN