4-Output 3.3V PCIe Zero-delay Buffer

文件：305.09 Kbytes 页数：19 Pages

IDT

4-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer

The 9DBL0452 4-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0452 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.\n\nFor information regarding evaluation boards and material, please contact your local s • Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)\n• 4 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair\n• Dedicated OE# pin for each output\n• Pin or SMBus configuration\n• SMBus interface not required for device operation\n• Space saving 32-pin 5 × 5 mm VFQFPN;

Renesas

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2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers

▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBL0x4x devices provide integrated 100Ω terminations ▪ 9DBL0x5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to other logic families ▪ Spread-spectrum compatible ▪ Dedicated OE

文件：1.42299 Mbytes 页数：33 Pages

RENESAS

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2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers

▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBL0x4x devices provide integrated 100Ω terminations ▪ 9DBL0x5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to other logic families ▪ Spread-spectrum compatible ▪ Dedicated OE

文件：1.42299 Mbytes 页数：33 Pages

RENESAS

瑞萨

4-Output 3.3V PCIe Zero-delay Buffer

文件：305.09 Kbytes 页数：19 Pages

IDT

4-output 3.3V PCIe Zero-delay Buffer

文件：305.76 Kbytes 页数：19 Pages

IDT

4-output 3.3V PCIe Zero-delay Buffer

文件：305.76 Kbytes 页数：19 Pages

IDT

4-Output 3.3V PCIe Zero-delay Buffer

文件：305.09 Kbytes 页数：19 Pages

IDT

Package：32-VFQFN 裸露焊盘；包装：管件 类别：集成电路（IC） 应用特定时钟/定时 描述：IC CLK BUFFER ZD 32-VFQFPN

RENESAS

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Package：32-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：IC CLK BUFFER ZD 32-VFQFPN

RENESAS

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