2-output 3.3V PCIe Zero-Delay Buffer

文件：300.42 Kbytes 页数：19 Pages

IDT

2-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer

The 9DBL0242 2-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0242 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures. • Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)\n• 2 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair\n• Dedicated OE# pin for each output\n• Pin or SMBus configuration\n• SMBus interface not required for device operation\n• Space saving 24-pin 4 × 4 mm VFQFPN;

Renesas

瑞萨

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.18 Kbytes 页数：19 Pages

IDT

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.42 Kbytes 页数：19 Pages

IDT

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.18 Kbytes 页数：19 Pages

IDT

2-output 3.3V PCIe Zero-Delay Buffer

文件：300.42 Kbytes 页数：19 Pages

IDT

Package：24-VFQFN 裸露焊盘；包装：管件 类别：集成电路（IC） 应用特定时钟/定时 描述：IC CLK FANOUT/BUFF ZD 24VFQFPN

RENESAS

瑞萨

Package：24-VFQFN 裸露焊盘；包装：管件 类别：集成电路（IC） 应用特定时钟/定时 描述：IC

RENESAS

瑞萨

Package：24-VFQFN 裸露焊盘；包装：管件 类别：集成电路（IC） 应用特定时钟/定时 描述：IC

RENESAS

瑞萨