2-output 3.3V PCIe Zero-Delay Buffer

文件：300.18 Kbytes 页数：19 Pages

IDT

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS

Features ▪ LOS open-drain output indicates loss of input clock ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to othe

文件：1.36054 Mbytes 页数：32 Pages

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瑞萨

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS

Features ▪ LOS open-drain output indicates loss of input clock ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to othe

文件：1.36054 Mbytes 页数：32 Pages

RENESAS

瑞萨

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS

Features ▪ LOS open-drain output indicates loss of input clock ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to othe

文件：1.36054 Mbytes 页数：32 Pages

RENESAS

瑞萨

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS

Features ▪ LOS open-drain output indicates loss of input clock ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to othe

文件：1.36054 Mbytes 页数：32 Pages

RENESAS

瑞萨

2 and 4-Output 3.3V PCIe Gen1–5 Clock Fanout Buffers with LOS

Description The 9DBL0255/9DBL0455 are 2 and 4-output PCIe Clock fan-out buffers for PCIe Gen1–5 applications. Both parts have an open drain Loss of Signal (LOS) output to indicate the absence or presence of an input clock. The LOS circuit also implements Automatic Clock Parking (ACP) to clean

文件：805.18 Kbytes 页数：17 Pages

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瑞萨

2 and 4-Output 3.3V PCIe Gen1–5 Clock Fanout Buffers with LOS

Description The 9DBL0255/9DBL0455 are 2 and 4-output PCIe Clock fan-out buffers for PCIe Gen1–5 applications. Both parts have an open drain Loss of Signal (LOS) output to indicate the absence or presence of an input clock. The LOS circuit also implements Automatic Clock Parking (ACP) to clean

文件：805.18 Kbytes 页数：17 Pages

RENESAS

瑞萨

2 and 4-Output 3.3V PCIe Gen1–5 Clock Fanout Buffers with LOS

Description The 9DBL0255/9DBL0455 are 2 and 4-output PCIe Clock fan-out buffers for PCIe Gen1–5 applications. Both parts have an open drain Loss of Signal (LOS) output to indicate the absence or presence of an input clock. The LOS circuit also implements Automatic Clock Parking (ACP) to clean

文件：805.18 Kbytes 页数：17 Pages

RENESAS

瑞萨

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers

Features ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to other logic families ▪ Spread-spectrum compatible ▪ Dedic

文件：1.37354 Mbytes 页数：32 Pages

RENESAS

瑞萨

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS

Features ▪ LOS open-drain output indicates loss of input clock ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to othe

文件：1.36054 Mbytes 页数：32 Pages

RENESAS

瑞萨