PLL or bypass mode

Description The 9DB833 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB833 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. Features/Benefits • 3 Selectable SMBus Add

文件：240.58 Kbytes 页数：18 Pages

IDT

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

Description The 9DB833 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB833 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. Features • 3 selectable SMBus addres

文件：407.82 Kbytes 页数：19 Pages

RENESAS

瑞萨

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

RENESAS

瑞萨

SMBus Interface; unused outputs can be disabled

Description The 9DB833 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB833 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. Features/Benefits • 3 Selectable SMBus Add

文件：240.58 Kbytes 页数：18 Pages

ICST

8-output 3.3 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

The 9DB833 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB833 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. Eight 0.7V HCSL differential output pairs\nPhase jitter: PCIe Gen3 < 1ps rms\nPhase jitter: PCIe Gen2 < 3.1ps rms\nPhase jitter: PCIe Gen1 < 86ps peak to peak\nSupports zero delay buffer mode and fanout mode\nBandwidth programming available\n3 selectable SMBus Addresses\n50-110 MHz operation in PLL ;

Renesas

瑞萨

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

RENESAS

瑞萨

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

RENESAS

瑞萨

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

RENESAS

瑞萨

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

RENESAS

瑞萨

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：375.65 Kbytes 页数：19 Pages

RENESAS

瑞萨