FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

Description The 9DB433 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. Features • 3 selectable SMBus addres

文件：431.97 Kbytes 页数：18 Pages

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FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：399.81 Kbytes 页数：18 Pages

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Spread Spectrum Compatible

文件：231.9 Kbytes 页数：17 Pages

IDT

SMBus Interface; unused outputs can be disabled

文件：231.9 Kbytes 页数：17 Pages

ICST

4-output 3.3 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

The 9DB433 zero delay buffer (ZDB) supports PCIe Gen3 requirements while being backward compatible with PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from a 932S421 or 932SQ420 or equivalent main clock generator. • Four 0.7V HCSL differential output pairs\n• Phase jitter: PCIe Gen2 < 3.1ps rms\n• Supports Zero Delay Buffer mode and Fanout mode\n• 33MHz to 110MHz operation in PLL mode\n• 10MHz to 110MHz operation in Bypass mode;

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FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：399.81 Kbytes 页数：18 Pages

RENESAS

瑞萨

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：399.81 Kbytes 页数：18 Pages

RENESAS

瑞萨

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：399.81 Kbytes 页数：18 Pages

RENESAS

瑞萨

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：399.81 Kbytes 页数：18 Pages

RENESAS

瑞萨

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

• 3 selectable SMBus addresses; multiple devices can share the same SMBus segment • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tra

文件：399.81 Kbytes 页数：18 Pages

RENESAS

瑞萨